1. Field of the Invention
The present invention relates to techniques for designing integrated circuits. More specifically, the present invention relates to a method and apparatus for placing an integrated circuit device within an integrated circuit layout.
2. Related Art
Systematic variations in transistor performance can arise during the process of fabricating an integrated circuit (IC) chip. These systematic variations become increasingly dominant in nanometer-scale semiconductor technologies. For example, variations in polysilicon pitch can lead to variations in the critical dimension of transistor gates and threshold voltages due to the optical effects in lithography and uneven amount of lateral polysilicon etching, which can have a significant impact on circuit performance. Similarly, variations in the placement of active diffusion regions can affect carrier mobility and threshold voltage as a result of changes in mechanical stress and transient enhanced impurity diffusion.
One technique for minimizing systematic variations is to impose regularity within an IC layout. For example, a fixed polysilicon pitch can be used to enforce regularity. This is achieved by requiring polysilicon lines to be placed on a fixed grid so that a polysilicon gate is placed in every grid location regardless of whether an IC device is to be created at the grid location. For example, FIG. 4 illustrates a typical standard cell IC layout wherein polysilicon lines are placed on a fixed grid. FIG. 4 includes active diffusion regions 400-405, polysilicon lines 406-414, and metal lines 415-416. Note that active diffusion regions 400-402 and active diffusion regions 403-405 can be different types of active diffusion regions. For example, active diffusion regions 400-402 can be p-type active diffusion regions and active diffusion regions 403-405 can be n-type active diffusion regions.
When a polysilicon line overlaps an active region, a transistor is formed. For example, in FIG. 4, transistors are formed when polysilicon lines 406-408 overlap active diffusion regions 400 and 403; polysilicon line 409 overlap active diffusion regions 401 and 404; and polysilicon lines 410-411 overlap active diffusion regions 402 and 405. However, note that polysilicon lines 412-414, which are referred to as “dummy polysilicon lines,” do not overlap any active diffusion regions and hence do not form any transistors. These dummy polysilicon lines 412-414 are used to maintain regularity in the IC layout.
As illustrated in FIG. 4, existing techniques use shallow trench isolation (STI) to separate one device from another (i.e., active IC devices separated by regions without active diffusion). However, when logic cells are placed in rows, there can be a lack of regularity across active diffusion regions. This is because each diffusion edge presents a discontinuity that can cause device property variations such as: threshold voltage changes due to transient enhanced diffusion; mobility changes due to mechanical stress; capacitance changes due to diffusion area variation; and resistance changes due to contact misalignment to source/drain diffusion areas.
Hence, what is needed is a method and an apparatus for placing IC devices within an IC layout without the problems described above.